ISL6227EVAL1【PDF 1/11 页】EVALUATION BOARD 1 ISL6227

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ISL6227EVAL1 DDR Evaluation Board Setup

Procedure

Application Note

June 2004

AN1067

This document describes the setup procedure for the

ISL6227 Evaluation Board DDR implementation. For

information about the dual switcher application, please refer

to the ISL6227EVAL2 Evaluation Board Setup Procedure.

General Description

The ISL6227 can control two output voltages adjustable from

0.9V to 5.5V. The ISL6227 combines two synchronous PWM

voltage regulators into a single IC. When the DDR pin is set

to high, it transforms the IC into a complete DDR application.

Channel 1 can be set at a fixed 300kHz forced PWM mode or

an automatic mode with hysteretic diode-emulation at light

load and constant-frequency PWM synchronous rectification

at heavy load, assure high efficiency over a wide range of

conditions. Channel 2 is set at fixed 300kHz forced PWM

mode with synchronous rectification because of sinking

current requirement for DDR applications. Both channels use

the lower MOSFET r DS(ON) as the current sense element for

high efficiency operations. It is preferred that the input of the

second channel connects to the output of the first channel in

DDR applications.

Voltage-feed-forward ramp modulation, current mode control,

and internal feedback compensation provide fast response to

input voltage and output load transients.

Features

? Provides regulated output voltage in the range of 0.9V–5.5V

- High efficiency over wide load range

- Synchronous buck converter with hysteretic operation at

light load

- Selection of hysteretic/CCM mode on channel 1. Forced

CCM on channel 2 for DDR application

? Uses MOSFET r DS(ON) for current sensing or uses

current-sense resistor for precision overcurrent protection

? Overvoltage, undervoltage and overcurrent protection

? Undervoltage lock-out on VCC pin

? Dual input voltage mode operation

- Operates directly from battery 5V to 24V input

- Operates from 3.3V or 5V system rail

? Excellent dynamic response

- Combined voltage feed-forward and current mode

control

? Power-good signal for channel 1 in DDR application

Ordering Information

ISL6227 monitors the output voltage of CH1 only by the

voltage on VSEN1 pin. PGOOD1 (power good) signal is

asserted after its soft-start sequence has completed, and the

output voltage within -11%/+15% of the set point. PGOOD2

pin is used to bring the VDDQ/2 into the chip as the

reference voltage of the second channel error amplifier.

PART #

ISL6227CA

ISL6227CAZ

(Note)

TEMP. (°C)

-10 to 100

PACKAGE

28 Ld SSOP

28 Ld SSOP (Lead-Free)

PKG

DWG #

M28.15

Built-in overvoltage protection prevents the output from

going above 115% of the set point by holding the lower

MOSFET on and the upper MOSFET off. When the output

voltage decays below the overvoltage threshold, normal

operation automatically resumes. Once the soft-start

sequence has completed, undervoltage protection will latch

the channel off if the output drops below 75% of its set point

value. There is no overvoltage protection for Channel 2 in

DDR application.

ISL6227CA-T -10 to 100 28 Ld SSOP Tape and Reel M28.15

ISL6227CAZ-T -10 to 100 28 Ld SSOP Tape and Reel M28.15

(Note) (Lead-Free)

NOTE: Intersil Lead-Free products employ special lead-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and lead-

free soldering operations. Intersil Lead-Free products are MSL

classified at lead-free peak reflow temperatures that meet or exceed

the lead-free requirements of IPC/JEDEC J Std-020B.

Adjustable overcurrent protection (OCP) monitors the

voltage drop across the r DS(ON) of the lower MOSFET. If

more precise current-sensing is required, an external current

sense resistor may be used. The OCP threshold can be

adjusted by the resistor on OCSET pin and the current

sensing gain can be adjusted by the resistor from ISEN pin

to the phase node of the converter. Any overcurrent on the

second channel will be reflected to the first channel. There is

no OCP for the second channel.

In order to alleviate the interaction between the two channels

caused by the switching noise, a phase shift has been

implemented on the controller. If the input voltage is above

5V, the VIN pin should connect the input voltage. This would

provide the input voltage feed forward function and

command the second channel 90 degree lagging the first

channel. If the input voltage is at 3.3V, the VIN pin should

connect to ground. This would result in a fixed ramp for the

PWM comparator and command an in-phase operation of

the two channels.

Pinout

ISL6227 (28 LD SSOP) TOP VIEW

GND 1 28 VCC

LGATE1 2 27 LGATE2

PGND1 3 26 PGND2

PHASE1 4 25 PHASE2

UGATE1 5 24 UGATE2

BOOT1 6 23 BOOT2

ISEN1 7 22 ISEN2

EN1 8 21 EN2

VOUT1 9 20 VOUT2

VSEN1 10 19 VSEN2

OCSET1 11 18 OCSET2

SOFT1 12 17 SOFT2

DDR 13 16 PG2/REF

VIN 14 15 PG1

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

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